The present invention pertains to magnetic domain memory devices and more particularly to a system which permits utilization of magnetic domain chips having one or more defective portions which are incapable of propagating magnetic domains.
In recent years tremendous progress has been made in developing equipment for electronic data processing such that today high speed reliable hardware is available to the data processing designer. The newly developed electronic components, particularly those using integrated circuits, have greatly increased the capacity of modern electronic data processing equipment to process data. As the speed and capacity of processing has increased, the data storage requirements have also increased. At present several different techniques exist for storing large quantities of digital data including punched cards, punched tape, magnetic tape, magnetic drums, magnetic disc, and magnetic cores. In all of these types of storage, with the exception of magnetic cores and their solid state storage counterparts, a relatively long period of time is required for accessing any particular bit of data.
On the other hand, with random access type memories such as provided with magnetic cores and their semiconductor counterparts, any particular bit or word stored in the memory can be retrieved extremely fast, the time required to read any stored bit of information being only the time required for the electronic circuits to operate. However, increased speed has also resulted in increased costs. As a consequence, considering in general the memories discussed above, the cost per bit of information stored is cheapest with the slowest devices and most expensive with the fastest devices. Accordingly, there has been an effort to develop large capacity memories which are characterized by a large data access time but which are less expensive than magnetic cores and solid state storage configurations.
In this regard, significant interest has developed recently in a class of magnetic devices generally referred to as magnetic domain devices or "magnetic bubbles". These devices are described, for example, in IEEE Transactions on Magnetics, Vol. MAG--5, No. 3 (1969), pp. 544-553, "Application or Orthoferrites to Domain-Wall Devices". These magnetic domain devices are generally planar in configuration and are constructed of materials which have magnetically easy directions which are essentially perpendicular to the plane of the structure. Magnetic properties such as magnetization anisotropy, coercivity, and mobility, are such that the device may be maintained magnetically saturated with magnetization in a direction out of the plane and that small localized single domain regions of magnetic polarization aligned opposite to the general polarization direction may be supported. Such localized regions which are generally cylindrical in configuration represent binary memory bits. Interest in these devices in large part is based on the high density that can be obtained and the ability of the cylindrical magnetic domains to be independent of the boundary of the magnetic material in the plane in which it is formed and hence they are capable of moving anywhere in the plane of the magnetic material to effect various data processing operations.
A magnetic domain can be manipulated by programming currents through a pattern of conductors positioned adjacent the magnetic material or by varying the surrounding magnetic field. As an example, the magnetic domains may be formed in thin platelets having uniaxial anisotropy with the easy magnetic axis perpendicular to the plate comprising such material as rare earth orthoferrites, rare earth aluminum and gallium substituted iron garnets and rare earth cobalt or iron amorphous alloys. Since the magnetic bubbles can be propagated, erased, replicated and manipulated to form data processing operations and their presence and absence detected, these bubbles may be utilized to perform the primary functions vital to memory operation.
Many structural organizations of operable magnetic domains have been disclosed in the literature. One of the most popular is the major-minor memory organization disclosed in U.S. Pat. No. 3,618,054. The major-minor loop memory organization as well as its implementation and operation is well known in the art. The major-minor loop organization includes a closed major loop which typically is established by an arrangement of T-bar permalloy circuits on, for example, a rare earth orthoferrite platelet. The magnetic domains are propagated around the loop by in-plane rotating magnetic field action. The major loop is generally elongated to permit a number of minor loops to be aligned along side it. Two way transfer gates permit the transfer of magnetic domains from the minor loop to the major loop and from the major loop to a minor loop. Further access to the major loop is achieved by a detect and read connection thereto and by a separate write connection.
The organization above described permits a synchronized domain pattern since propagation in the loops is synchronous with the rotation of the in-plane field. That is, parallel transfer of data domains from a plurality of minor loops may be made simultaneously to the major loop. Moreover, a plurality of data chips, each with a major loop and a plurality of associated minor loops, may be treated together. It is common to arrange such data chips in rows and then even to stack rows of data chips in time multiplexed layers to achieve complex memory structures, the data domains in all the loops and all the chips being synchronized with in-plane rotations.
Typically, all of the minor loops in the chip, upon command, transfer in parallel the bubbles from their corresponding positions to the major loop. The bubbles are then serially detected as they are propagated past a read position. New data may also be inserted at a write position for parallel transfer back into the minor loops at an appropriate time later (when major loop magnetic domain propagation aligns the data for transfer).
Simultaneous reading/writing of data into a grouping of related major loops gives the capacity of treating related magnetic domains as digital or other coded words. Time multiplexed groups of data chips permits reading and writing of data in a time sharing fashion to permit an overall memory data rate greater than that permitted by magnetic domain propagation in a single chip.
Although a bubble memory system employing major-minor loops of the type described has numerous economic and operational advantages, unless special provision is made, every loop in every chip of the system must be perfect for the system to perform in a satisfactory manner. Since chips contain entire groupings of registers, a defect in one of the minor loops would require discarding the entire chip. Various techniques have been proposed in the art for permitting use of a magnetic domain chip even though one or more of its minor loops may be defective. Exemplary techniques are described, for example, in U.S. Pat. No. 3,909,810, entitled "Bubble Memory Minor Loop Redundancy Scheme", which is assigned to the assignee of the present invention and "Fault-Tolerant Memory Organization: Impact on Chip Yield and System Cost", IEEE Transactions Magnetics, September, 1974. These techniques utilize a magnetic domain chip to store locations of defective loops. This technique, that is storing defective loop locations on a magnetic domain chip, is subject to loss of accuracy with time and it would be advantageous if defective loop location information could be stored in a non-volatile semiconductor memory.
A further example of techniques to overcome this deficiency is found in co-pending patent application Ser. No. 594,901, filed July 10, 1975, now U.S. Pat. No. 4,070,651 issued Jan. 24, 1978. The technique described therein is an important step in development of a system using data chips with defective minor loops. Generally, what is disclosed is using a non-volatile semiconductor memory such as a programmable read-only-memory to store the relative positions of defective minor loops to each other. This data is used to control logic so that a stream of data bubbles to be transferred into the minor loops for storage, for example, contain intermittent voids corresponding to defective minor loop locations. Although the invention disclosed in the aforesaid patent application Ser. No. 594,901, now U.S. Pat. No. 4,070,651, is advantageous over the technique of storing the defective minor loop locations in a magnetic domain chip, it stops short of allowing flexibility in data chip replacement without the cumbersome procedure of removing the obsolete programmable read-only-memory and replacing it with a newly programmed unit each time a bubble chip is replaced in the system. This method includes manually addressing the programmable read-only device with data representing the locations for all defective minor loops in the system and not just those on the new chip.
A further problem inherent in the device disclosed in the above application (Ser. No. 594,901), now U.S. Pat. No. 4,070,651, is the loss of additional minor loops where the number of adjacent perfect minor loops exceeds fifteen. In that system the maximum binary digit that could be stored was a four bit word and resulted in a maximum number of `1111` or fifteen which told the logic to skip fifteen good loops and prevent data from being stored in the next minor loop.